1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a MOSFET having a gate structure formed by a replacement technique.
2. Description of the Background Art
FIG. 34 is a cross-sectional view of a background art semiconductor device having a gate structure formed by the replacement technique. As shown in FIG. 34, the background art semiconductor device comprises: a silicon substrate 101; a pair of spaced source/drain regions 109 formed in an upper surface of the silicon substrate 101 and defining a channel region (not shown) therebetween in the upper surface of the silicon substrate 101; a pair of sidewalls 107 and a pair of silicon nitride films 108 which are formed on the upper surface of the silicon substrate 101 so as to overlie the source/drain regions 109; and a gate structure 106 formed in a recess defined by the upper surface of the silicon substrate 101 over the channel region and side surfaces of the sidewalls 107. The gate structure 106 comprises a gate oxide film 102 formed on the upper surface of the silicon substrate 101, and a gate electrode including a polysilicon film 103 formed on the gate oxide film 102, a barrier metal 104 formed on the side surfaces of the sidewalls 107 and an upper surface of the polysilicon film 103, and a metal film 105 formed on the barrier metal 104.
FIGS. 35 through 41 are cross-sectional views showing a method of manufacturing the background art semiconductor device shown in FIG. 34 in a step-by-step manner. Initially, an isolating insulation film (not shown) is formed in an isolation region of the silicon substrate 101, and thereafter ion implantation is performed to form a well, a doped channel region and the like (not shown). Then, a silicon oxide film 110, a polysilicon film 111 and a silicon oxide film 112 are formed by deposition or the like in stacked relation in the order named on the upper surface of the silicon substrate 101 (FIG. 35).
Next, a photoresist 113 is formed by a photolithographic technique on an upper surface of the silicon oxide film 112 over a region in which a dummy gate electrode is to be formed later (FIG. 36). Using the photoresist 113 as a mask, the silicon oxide film 112, the polysilicon film 111 and the silicon oxide film 110 are etched in the order named to expose the upper surface of the silicon substrate 101. Then, the photoresist 113 is removed. This provides the gate oxide film 102 selectively formed on the upper surface of the silicon substrate 101, and the dummy gate electrode formed on the gate oxide film 102 and having a multilayer structure including the polysilicon film 103 and a silicon oxide film 114 which are stacked in the order named. Thereafter, using the dummy gate electrode as a mask, ions 115 are implanted into the upper surface of the silicon substrate 101 to form a pair of extension regions 116 (FIG. 37).
A silicon nitride film is deposited on the entire surface of the resultant structure, and is etched back until the upper surface of the silicon substrate 101 is exposed, to form the sidewalls 107 on side surfaces of the dummy gate electrode. Using the dummy gate electrode and the sidewalls 107 as a mask, ions 117 are implanted into the upper surface of the silicon substrate 101 to form the pair of source/drain regions 109 (FIG. 38).
A silicon nitride film is deposited on the entire surface of the resultant structure, and is polished until an upper surface of the silicon oxide film 114 is exposed, to form the silicon nitride films 108 (FIG. 39). Using the silicon nitride films 108 as a mask, the silicon oxide film 114 is etched away to expose the upper surface of the polysilicon film 103 (FIG. 40). A barrier metal 118 and a metal film 119 are deposited on the entire surface of the resultant structure (FIG. 41). Next, the barrier metal 118 and the metal film 119 are polished until the upper surface of the silicon nitride films 108 is exposed by a CMP process. This provides the structure shown in FIG. 34. After the steps of forming an interlayer insulation film and forming an interconnect line and the like, the device is completed.
However, the background art semiconductor device and the method of manufacturing the same present problems to be described below.
Reductions in gate length and in gate resistance are important factors required to increase the operating speed of a MOSFET or to improve the driving capability and high frequency characteristic thereof. The reduction in gate length is attained by forming a narrower photoresist pattern by a photolithographic technique, but there is a limit on the formation of fine patterns because of an exposure limit. For example, if the photoresist 113 having a length L101 is formed in the step shown in FIG. 36, the gate length L100 of the gate electrode equals the length L101 as shown in FIG. 34. Thus, a first problem with the background art semiconductor device and the method of manufacturing the same is that it is impracticable that the gate length which is determined by the exposure limit of the photolithographic technique used in the formation of the photoresist 113 is less than the exposure limit of the photolithographic technique.
On the other hand, the reduction in gate resistance of the background art semiconductor device shown in FIG. 34 is attained by making the lengths of the barrier metal 104 and the metal film 105 greater than the length of the polysilicon film 103 (equal to the gate length L100). However, according to the method of manufacturing the background art semiconductor device in which the lengths of the barrier metal 104 and the metal film 105 are equal to the gate length L100, the increase in the lengths of the barrier metal 104 and the metal film 105 requires the increase in the gate length L100 itself, presenting a second problem in that the driving capability of the MOSFET decreases.
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) selectively forming a multilayer structure including a gate insulation film and a dummy gate electrode stacked in the order named on an upper surface of a substrate, the dummy gate electrode having an upper part and a lower part; (b) forming a first insulation film in a side surface of the lower part; (c) forming a pair of source/drain regions in the upper surface of the substrate, with part of the upper surface of the substrate which underlies the gate insulation film lying between the pair of source/drain regions; (d) forming a second insulation film on the upper surface of the substrate overlying the pair of source/drain regions, the second insulation film having a thickness greater than the height of the first insulation film from the upper surface of the substrate, the second insulation film being in contact with the dummy gate electrode; (e) removing the dummy gate electrode while leaving the first insulation film, the step (e) being performed after the step (d); and (f) forming a gate electrode filling a recess defined by the gate insulation film and the first and second insulation films.
Preferably, according to a second aspect of the present invention, in the method of the first aspect, a thermal oxidation reaction proceeds at a lower rate in the upper part than in the lower part in the step (a). The first insulation film is formed by thermally oxidizing the dummy gate electrode in the step (b).
Preferably, according to a third aspect of the present invention, the method of the second aspect further comprises the step of (x) introducing an impurity into the upper surface of the substrate by using the dummy gate electrode as a mask to form an extension region, the step (x) being performed between the steps (a) and (b).
Preferably, according to a fourth aspect of the present invention, in the method of the second aspect, only the upper part is doped with an impurity having an oxidation inhibiting effect in the step (a).
Preferably, according to a fifth aspect of the present invention, in the method of the second aspect, only the lower part is doped with an impurity having an oxidation promoting effect in the step (a).
Preferably, according to a sixth aspect of the present invention, in the method of the second aspect, the dummy gate electrode formed in the step (a) has the lower part made of a first material which is thermally oxidizable, and the upper part made of a second material which is not thermally oxidizable.
Preferably, according to a seventh aspect of the present invention, in the method of the sixth aspect, the step (a) comprises the steps of: (a-1) forming a polysilicon film of the first material and a silicon oxide film of the second material in stacked relation in the order named on the entire upper surface of the substrate; (a-2) etching away the silicon oxide film except where the dummy gate electrode is to be formed; and (a-3) etching away the polysilicon film by using the silicon oxide film as a mask, the step (a-3) being performed after the step (a-2).
According to an eighth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) preparing a structure including a pair of spaced source/drain regions formed in an upper surface of a substrate, and a mask formed on the upper surface of the substrate and having an opening over a region lying between the pair of source/drain regions; and (b) introducing an impurity through the mask into the substrate.
Preferably, according to a ninth aspect of the present invention, in the method of the eighth aspect, the impurity is introduced into the substrate in step (b) by ion implantation angled with respect to the normal to the upper surface of the substrate.
Preferably, according to a tenth aspect of the present invention, in the method of the ninth aspect, the step (a) comprises the steps of: (a-1) selectively forming a dummy gate structure on the upper surface of the substrate; (a-2) forming the pair of source/drain regions in part of the upper surface of the substrate which is not covered with the dummy gate structure; (a-3) forming an insulation film serving as the mask on the upper surface of the substrate overlying the pair of source/drain regions, the insulation film being in contact with the dummy gate structure; and (a-4) removing the dummy gate structure, the step (a-4) being performed after the step (a-3). The method further comprises the step of (c) forming a gate structure filling the opening of the mask, the step (c) being performed after the step (b).
In accordance with the first aspect of the present invention, the gate length of a lower part of the gate electrode is made smaller than the gate length of an upper part thereof by the total width of the first insulation film. Therefore, the method of the first aspect can increase the operating speed of the semiconductor device and improve the high frequency characteristic thereof without decreasing the driving capability thereof.
In accordance with the second aspect of the present invention, the dummy gate electrode such that the thermal oxidation reaction proceeds at a lower rate in the upper part thereof than in the lower part thereof is formed in the step (a). This allows a simple thermal oxidation process to form the first insulation film in the lower part of the side surface of the dummy gate electrode.
In accordance with the third aspect of the present invention, the extension region is formed in the upper surface of the substrate before the step (b). Therefore, the thermal oxidation process in the step (b) causes the impurity in the extension region to thermally diffuse, forming an extension diffusion region.
In accordance with the fourth aspect of the present invention, the impurity having the oxidation inhibiting effect is introduced into only the upper part of the dummy gate electrode to inhibit the thermal oxidation reaction from proceeding in the upper part of the dummy gate electrode. Therefore, the method of the fourth aspect can suitably form the first insulation film in the lower part of the side surface of the dummy gate electrode.
In accordance with the fifth aspect of the present invention, the impurity having the oxidation promoting effect is introduced into only the lower part of the dummy gate electrode to promote the thermal oxidation reaction in the lower part of the dummy gate electrode. Therefore, the method of the fifth aspect can suitably form the first insulation film in the lower part of the side surface of the dummy gate electrode. Additionally, the method of the fifth aspect can reduce the oxidation time for the formation of the first insulation film, as compared with the method of the fourth aspect, to prevent the impurity, if introduced into the substrate, from being excessively thermally diffused.
In accordance with the sixth aspect of the present invention, the dummy gate electrode having the lower part made of the first material which is thermally oxidizable and the upper part made of the second material which is not thermally oxidizable is formed in the step (a). This allows a simple thermal oxidation process to form the first insulation film only in the lower part of the side surface of the dummy gate electrode. Additionally, since the upper part of the dummy gate electrode is not thermally oxidized, the method of the sixth aspect can form the gate electrode equal in size to the dummy gate electrode to set the value of the gate resistance precisely and easily.
In accordance with the seventh aspect of the present invention, polysilicon is adopted as the first material of the lower part of the dummy gate electrode, and silicon oxide having a higher selectivity to polysilicon than other materials such as silicon nitride is adopted as the second material of the upper part of the dummy gate electrode. Since the silicon oxide film is hardly etched in the step (a-3), the silicon oxide film need not be formed so thick in the step (a-1), and etching of the silicon oxide film in the step (a-2) is easily controlled.
In accordance with the eighth aspect of the present invention, the step (a) of forming the source/drain regions is followed by the step (b) of introducing the impurity into the substrate to form a doped region. Therefore, the impurity introduced into the doped region is not affected by the heat treatment for the formation of the source/drain regions. This prevents the doped region from being formed in a deeper position in the substrate and the resistance of the doped region from increasing.
In accordance with the ninth aspect of the present invention, the impurity ion implantation angled with respect to the normal to the upper surface of the substrate is preferred to form pocket regions near the confronting ends of the pair of source/drain regions, respectively.
In accordance with the tenth aspect of the present invention, the mask against ion implantation is used to form the gate structure in a self-aligned fashion.
It is therefore an object of the present invention to attain the reduction in gate length of a semiconductor device having a gate structure formed by a replacement technique without the decrease in driving capability of the semiconductor device, thereby to provide a method of manufacturing the semiconductor device which can increase the operating speed thereof and improve the high frequency characteristic thereof.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.